1. Field of the Invention
The present invention relates to a semiconductor apparatus having a transistor and a manufacturing method thereof. In particular, the present invention relates to a semiconductor apparatus that stabilizes characteristics of a transistor in a triple well of the semiconductor apparatus having a triple-well structure and a manufacturing method thereof.
2. Description of the Related Art
In order to realize the design of low consumption power of an LSI (Large Scale Integration) circuit, a CMOS circuit is generally used as the LSI circuit. The CMOS circuit comprises a P-channel MOS (PMOS) transistor and an N-channel MOS (NMOS) transistor. The PMOS transistor is arranged to an N-type well (N-well) region, and the NMOS transistor is arranged to a P-type well (P-well) region.
For a semiconductor apparatus in which noises to the P-well region need to be suppressed from a semiconductor substrate except for the P-well region and a semiconductor apparatus in which the injection of current of minority carrier on a semiconductor substrate except for the P-well region to the P-well region needs to be suppressed, a triple-well structure is used for surrounding the circumference of the P-well region in a P-type semiconductor substrate with the N-well region.
Because the N-well region surrounding the circumference of the P-well region functions as electrical insulation of the P-type substrate and the P-well region so as to suppress the noises from the semiconductor substrate and prevent the injection of current of minority carrier in the semiconductor substrate.
The above-mentioned semiconductor apparatus includes, e.g., a semiconductor apparatus concerned with a memory and a semiconductor apparatus that uses a plurality of signals at different logical levels.
However, if using the triple-well structure that includes all the P-well regions in the N-well region, a contact region for supplying potentials to the P-well region needs to be ensured on the surfaces of the P-well regions on the semiconductor substrate, independently of an MOS transistor region, and a problem for increasing the chip area is caused.
Then, in order to supply the potentials to the P-well regions surrounded by the N-well region and electrically connect the bottoms of the P-well regions to the semiconductor substrate, it is proposed that a through-hole pierced through the N-well region is arranged.
As a consequence, a predetermined potential level is supplied to the P-well region from the semiconductor substrate without causing the problem for increasing the chip area while keeping the advantage for preventing the noises from the semiconductor substrate and the injection of the current of minority carrier on the semiconductor substrate.
As disclosed in Patent Document 1, upon forming the through-hole pierced through the N-well region, it is necessary that an N-type-impurity is not guided to the through-hole (case 1). Alternatively, it is necessary that a P-type impurity is guided to a region of the through-hole so as to compensate for the N-type-impurity guided to the region of the through-hole (case 2).
Further, in order to prevent the influence to the P-well surface on the top from the impurity guided to form the through-hole pierced through the N-well region, the following requirements should be satisfied. In the case 1, the guiding of the impurity needs not to be completely prevented outside the border line of the region of the through-hole and, on the other hand, the guiding of the impurity needs to be completely shut-off inside the border line. In the case 2, on the contrary, the guiding of the impurity needs to be completely shut-off outside the border line of the region of the through-hole and, on the other hand, the guiding of the impurity needs not to be completely prevented inside the border line.
However, the above operation is not possible by setting, as a mask, resist patterned to prevent the guiding of the impurity, arranged at the border of the region of the through-hole. As a consequence, at the border portion of the region of the through-hole, the incompletely-guided impurity is distributed from the bottom of the P-well region to the surface of the P-well region. Therefore, the concentration of the impurity at the P-well region at the border portion of the through-hole region is not constant. Accordingly, characteristics of a transistor formed at the border portion of the through-hole region, such as current leakage characteristics between terminals of the transistor, are harmfully influenced from the concentration of the impurity at the border portion of the through-hole region.